Digital-analog converting method, and apparatus therefor

ABSTRACT

A continuous analog signal is produced by successively generating digital data V K  (K=. . . , -4, -3, -2, -1, 0, 1, 2, 3, . . . ) every predetermined sampling period T, repeatedly generating, successively at a period 3T, signals φ(t+T), φ(t), φ(t-T), where a unit pulse response signal ψ(t) is expressed by 
     
         ψ(t)=ΣA.sub.K ·φ(t-K·T) 
    
      (K=-∞˜+∞) 
     using a signal φ(t) (0≦t≦3·T) expressed by three piecewise polynomials, computing C in accordance with the equation 
     
         C=ΣA.sub.-K ·V.sub.K (K=-M˜m) 
    
     every sampling period T, where V 0  represents digital data prevailing at the present time, cyclically storing the results of computation as C -1 , C 0 , C 1  in successive fashion, and converting the digital data into an analog quantity in accordance with the equation 
     
         C.sub.-1 ·φ(t+T)+C.sub.2 ·φ(t)+C.sub.3 
    
      ·φ(t-T)

BACKGROUND OF THE INVENTION

This invention relates to a digital-analog converting method and apparatus, and more particularly, to a digital-analog converting method and apparatus suitable for use in converting a digital audio signal into an analog audio signal.

In compact disc players (CD players) or digital tape recording/playback devices (DAT devices), it is required that musical signals expressed in digital form be converted into analog signals prior to output.

As shown in FIG. 12, a commonly employed digital-analog converter (hereinafter referred to as a "DA converter") for playing back music includes a digital current converter 1 for converting digital data DT, which is inputted at a certain sampling period, into a direct current I_(o), a current-voltage converter 2 for converting the current I_(o) into a voltage S_(D) (see FIG. 13), and for holding the voltage, each time a sampling pulse P_(s) is generated, and a low-pass filter 3 for forming the output voltage S_(D) into a continuous, smooth analog signal S_(A), which is the output of the filter 3. The current-voltage converter 2 includes a switch SW having a movable contact changed over by the sampling pulse P_(s). When the movable contact is switched to a contact a, as shown in FIG. 12, an integrator is formed to generate the voltage S_(D), which conforms to the current I_(o). When the movable contact is switched to a contact b, a holding circuit is formed to hold the voltage S_(D).

The foremost problems encountered in the DA converter for music playback are the precision with which the digital data is converted into a current value, the speed at which the conversion is made and phase distortion caused by the low-pass filter.

The problems of conversion precision and conversion speed have largely been solved by higher speed LSI's and advances in trimming techniques. Though phase distortion ascribable to the low-pass filter can be mitigated by employing a digital filter, phase distortion cannot be eliminated completely so long as the filter is an integral part of the structure.

FIG. 14 is useful in describing phase distortion. FIG. 14(a) illustrates an original audio signal waveform 5a, a 1 KHz component waveform 5b, and an 8 KHz component waveform 5c. FIG. 14(b) illustrates an audio signal waveform 6a outputted by the low-pass filter 3 (FIG. 12), a 1 KHz component waveform 6b, and an 8 KHz component waveform 6c. It will be understood from these waveforms that, due to the delay in the phase of the 8 KHz component, the output audio signal 6a is different from the original audio signal 5a, and that this phase distortion becomes particularly pronounced at high frequencies. Thus, the presence of the low-pass filter results in a major deterioration in sound quality.

As shown in FIG. 15, the low-pass filter output when a pulsed signal is applied to the filter is sluggish at a leading edge 7a and oscillates at an envelope portion 7b and trailing edge 7c. Consequently, when a musical signal exhibiting a large impulse variation is applied to the low-pass filter, sound quality changes greatly and there are times when even the rhythmical sense of the musical signal differs.

To overcome these disadvantages, the inventors have proposed a digital-analog converter which, as shown in FIG. 16, includes a unit pulse response signal generator 1' for generating unit pulse response signals SP (see FIG. 17), a digital data generator 2' for generating 16-bit digital audio data at a predetermined time interval ΔT, a multiplier 3' for multiplying a unit pulse response signal generated at a certain time by a predetermined item of the digital audio data, and a mixer 4' for producing an analog signal output by combining the unit pulse response signals that have been multiplied by the digital audio data. By way of example, refer to the specification of U.S. Ser. No. 171,812 (entitled "Digital-Analog Converter", filed on Mar. 22, 1988).

In accordance with this proposed digital-analog converter, the unit pulse response generator 1' partitions a unit pulse response signal SP at a predetermined time interval ΔT (see FIG. 17). When this is done, partial signals S_(K), which result from the partitioning operation, are repeatedly generated at the time interval ΔT, as shown in FIG. 18 (where only S₋₁, S₀ and S₁ are illustrated). The digital data generator 2' stores 16-bit digital audio data V_(K), which is generated at the predetermined time interval ΔT, in internal shift registers while sequentially shifting the same. Multiplying-type DA converters in the multiplier 3' respectively multiply the partial signals S_(K) by predetermined 16-bit digital audio data V_(-K) stored in the shift registers corresponding to the partial signals. The mixer 4' combines the signals outputted by the multiplying-type DA converters, thereby producing an analog signal output S_(A) (=ΣS_(K) ·V_(-K)). This digital-analog converter makes it possible to generate a continuous analog signal that is free of phase distortion.

The proposed digital-analog converter takes into consideration the fact that the unit pulse response signal (FIG. 17) is sharply attentuated prior to a time slot T₋₅ and after a time slot T₅, and approximates the unit pulse response signal SP by nine partial signals S₋₄ through S₄ in nine time slots S₋₄ through S₄, respectively. For this reason, the proposed digital-analog converter requires nine partial signal generators, a memory circuit composed of nine shift registers, and nine multiplying-type DA converters. This is disadvantageous in terms of an increase in size and cost. If it is attempted to approximate the unit pulse response signal by a fewer number of partial signals in an effort to reduce the number of partial signal generators, the number of shift registers in the memory circuit and the number of multiplying-type DA converters, a new problem will arise in which the frequency characteristic of the analog signal output of the digital-analog converter undergoes a fluctuation in level in the audible band, as shown in FIG. 19.

Further, the partial signal waveforms S_(K) inputted to the multiplying-type DA converters in the proposed digital-analog converters become discontinuous at the interval ΔT, as shown in FIG. 18. A problem that arises is that, due to this signal discontinuity and the settling time of the multiplying-type DA converters, the analog signal S_(A) outputted by the mixer 4' picks up spike-shaped noise every ΔT. Moreover, the waveform of the analog signal S_(A) when a unit pulse UP is inputted to the proposed digital-analog converter is as shown in FIG. 20. Though the analog signal S_(A) must take on the waveform shown in FIG. 17 in a case where the unit pulse UP is applied, the waveform that results is one in which the analog signal picks up spike noise every ΔT owing the settling time of the multiplying-type DA converters.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a digital-analog converting method and apparatus capable of generating a continuous analog signal that is free of phase distortion.

Another object of the present invention is to provide a digital-analog converting method and apparatus through which it is possible to reduce the number of circuit units such as the multiplying-type DA converters, improve the S/N ratio and produce a flat frequency characeristic, namely one in which there is no level fluctuation in the audible band.

Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a digital-analog converter for realizing the system of the present invention;

FIGS. 2 through 9 are views useful in describing the principle of the invention, in which:

FIG. 2 is a view for describing time slots in a case where a time axis is divided at intervals of ΔT,

FIG. 3 is a view for describing digital data in each time slot,

FIG. 4 is a signal waveform diagram of one embodiment of unit pulse response,

FIG. 5 is a pulse response signal waveform diagram corresponding to three continuous digital signals,

FIG. 6 is a waveform diagram of a function φ_(K) (t) when a unit pulse response signal is expressed by ΣA_(K) φ_(K) (t),

FIG. 7(a) shows waveform diagrams of φ₋₁ (t), φ₀ (t) and φ₁ (t),

FIG. 7(b) shows a waveform diagram of A_(K) φ_(K) (t);

FIG. 8 shows pulse response signal waveform diagrams for three continuous digital signals V₋₁, V₀, V₁, and

FIG. 9 is a view for describing coefficient totaling processing performed by a digital signal processor;

FIG. 10 is a functional block diagram illustrating the processing performed by the digital signal processor;

FIG. 11 is a block diagram of a function generator;

FIG. 12 is a block diagram of a digital-analog converter according to the prior art;

FIG. 13 is a waveform diagram of waveforms associated with the converter of FIG. 12;

FIGS. 14 and 15 are views for describing phase distortion and waveform distortion in the digital-analog converter of the prior art;

FIGS. 16 through 18 are views for describing the general features of a proposed digital-analog converter;

FIG. 19 is a frequency characteristic for describing the drawbacks of the prior art; and

FIG. 20 is a waveform diagram for describing the drawbacks of the prior art.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The principle of the invention will now be described in accordance with FIGS. 2 through 9, after which a digital-analog converter according to the invention will be described in accordance with FIG. 1.

If a time axis is divided at a predetermined time interval T, as shown in FIG. 2, and a discrete time signal value (digital value) in each time slot T_(K) (K=T₋₄, T₋₃, T₋₂, T₋₁, T₀, T₁, T₂, T₃, T₄, . . . ) is designated by V_(K), as shown in FIG. 3, then a continuous signal conforming to the discrete time signals RTS is obtained by superposing, along the time axis, pulse response signals weighted by the digital data V_(K) inputted from one moment to the next.

FIG. 4(a) shows a unit pulse in the time slot T₀, and FIG. 4(b) is a waveform diagram illustrating a unit pulse response signal SP corresponding to the unit pulse signal. The waveform of signal SP is a spline signal waveform illustrative of an embodiment of the invention. It should be noted that the unit pulse response signal covers an interval extending from -∞ to +∞ on the time axis and is sharply attenuated from the time slot T₀ toward -∞ and +∞.

Focusing solely on the digital data V₋₁, V₀, V₁ in the time slots T₋₁, T₀, T₁ of the discrete time signals RTS shown in FIG. 3, it is seen that the pulse response signals SP₋₁, SP₀, SP₁ corresponding to the digital data V₋₁, V₀, V₁ are as indicated by the dashed line, solid line and one-dot chain line, respectively, shown in FIG. 5. Therefore, by combining these pulse response signals in order every T starting from the old time slot T_(K) (K=-∞, . . . -2, -1, 0, 1, 2, . . . ) and outputting the result, a continuous time signal corresponding to the three items of digital data V₋₁, V₀, V₁ is obtained. Note that the pulse response signals SP₋₁, SP₀, SP₁ in FIG. 5 are the result of multiplying the unit pulse response signal SP [see FIG. 4(b)] by V₋ 1, V₀, V₁, respectively.

The foregoing refers to three items of digital data. However, a continuous time signal can be obtained in similar fashion even when the digital data in all of the time slots are considered. In view of the fact that the pulse response signals are sharply attenuated, it will suffice if the number of pulse response signals to be combined in each time slot is nine at most. In other words, let T_(K) represent the present time slot. If the pulse response signals corresponding to the nine items of digital data in the time slots T_(K-4) through T_(K+4) are combined, a sufficiently accurate continuous time signal is obtained in time slot T_(K).

However, in accordance with the method of combining the pulse response waveforms corresponding to the nine items of digital data, as described earlier, nine circuit units are required, thereby resulting in a larger and more costly apparatus, and the unit pulse response signal waveforms are of a complicated nature so that the signals are discontinuous, the analog signal picks up noise and a high S/N ratio is required.

Accordingly, if the unit pulse response signal SP can be expressed using simpler function signals in short intervals, then the function signals can be used directly without being partitioned. This will eleiminate discontinuity and make it possible to reduce the number of circuit units required.

A function ψ(t) illustrating the unit pulse response signal SP shown in FIG. 4(b) can be expressed by the following equations using another function φ_(K) (t):

    ψ(t)=ΣA.sub.K ·φ.sub.K (t) (K=-∞˜+∞)                               (1)

    A.sub.K =√2(-3+2√2).sup.|K|(2)

Here φ(t) has a waveform in which three sampling times 3T constitute one period, as shown in FIG. 6, and is expressed by three piecewise polynomials. That is, φ(t) can be expressed as follows:

    φ(t)=(9/2)·(t/3T).sup.2 (0≦t<T)

    φ(t)=-9·(t/3T-1/2).sup.2 +3/4 (T≦t<2T)

    φ(t)=(9/2)·(t/3T-1).sup.2 (2T≦t<3T)

Further, if the function indicated by the solid line from time 0 to 3T is expressed by φ₀ (t), a function m sampling times earlier is expressed by φ_(-m) (t) and a function m sampling times later is expressed by φ_(m) (t), then we may write

    φ.sub.-m (t)=φ.sub.0 (t+m·T)              (3)

    φ.sub.m (t)=φ.sub.0 (t-m·T)               (4)

Calculating the coefficients A_(K) from Eq. (2) gives

    A.sub.-4 =A.sub.4 =√2(-3+2√2).sup.4 =0.0012727

    A.sub.-3 =A.sub.3 =√2(-3+2√2).sup.3 =-0.0071488

    A.sub.-2 =A.sub.2 =√2(-3+2√2).sup.2 =0.041632

    A.sub.-1 =A.sub.1 =√2(-3+2√2).sup.1 =-0.24264

    A.sub.0 =√2(-3+2√2).sup.0 =1.41421

Therefore, A_(K) φ_(K) (t) (K-∞˜+∞) in Eq. (1) becomes as shown in FIG. 7(b) (where only the waveforms for K=-1, 0, 1 are depicted). When these are combined, a unit pulse response signal (t) is obtained, as indicated by the dashed line.

If three items of digital data which are continuous in the sampling period T are expressed by . . . , V-1, V0, V1, . . . in order from the oldest to the newest, then the pulse response signals . . . , ψ₋₁ (t), ψ₀ (t), ψ₁ (t), . . . can be written as follows using Eqs. (1)-(4), respectively: ##EQU1## The result is as shown in FIG. 8. It should be noted that the items of digital data V₋₁, V₀, V₁ are illustrated as having identical values in FIG. 8.

Extracting the coefficients of the function φ₀ (t) from Eqs. (5) through (7) gives us

    V.sub.-1 ·A.sub.1, V.sub.0 ·A.sub.0, V.sub.1 ·A.sub.-1

In the foregoing, only the three items of data V₋₁, V₀, V₁ are considered. If nine items of continuous digital data V₋₄ -V₄ are taken into consideration, the coefficients of the function φ₀ (t) become as follows, as illustrated in FIG. 9:

    V.sub.4 A.sub.-4, V.sub.3 A.sub.-3, V.sub.2 A.sub.-2, V.sub.1 A.sub.-1, V.sub.0 A.sub.0,

    V.sub.-1 A.sub.1, V.sub.-2 A.sub.2, V.sub.-3 A.sub.3, V.sub.-4 A.sub.4(8)

Similarly, extracting the coefficients of the function φ₀ (t+T) from Eqs. (5) through (7) gives us

    V.sub.-1 ·A.sub.0, V.sub.0 ·A.sub.-1

If nine items of continuous digital data are taken into consideration, the coefficients of the function φ₀ (t+T) become as follows, as illustrated in FIG. 9:

    V.sub.3 A.sub.-4, V.sub.2 A.sub.-3, V.sub.1 A.sub.-2, V.sub.0 A.sub.-1, V.sub.-1 A.sub.0,

    V.sub.-2 A.sub.1, V.sub.-3 A.sub.2, V.sub.-4 A.sub.3, V.sub.-5 A.sub.4(9)

Further, extracting the coefficients of the function φ₀ (t-T) from Eqs. (5) through (7) gives us

    V.sub.0 ·A.sub.1, V.sub.1 ·A.sub.0

If nine items of continuous digital data are taken into consideration, the coefficients of the function φ₀ (t-T) become as follows, as illustrated in FIG. 9:

    V.sub.5 A.sub.-4, V.sub.4 A.sub.-3, V.sub.3 A.sub.-2, V.sub.2 A.sub.-1, V.sub.1 A.sub.0,

    V.sub.0 A.sub.1, V.sub.-1 A.sub.2, V.sub.-2 A.sub.3, V.sub.-3 A.sub.4(10)

Thus, if the result of totaling the coefficients shown in Eq. (9) and multiplying the function φ(t+T) by the total, the result of totaling the coefficients shown in Eq. (8) and multiplying the function φ(t) by the total, and the result of totaling the coefficients shown in Eq. (10) and multiplying the function φ(t-T) by the total are combined to produce an output, a continuous analog signal corresponding to a series of digital data can be obtained.

A digital-analog converter in accordance with the present invention will now be described with reference to FIG. 1. Shown in FIG. 1 are a register 11 for storing digital data, a digital signal processor (DSP) 12, a latch section 13 having three latch circuits 13₋₁ -13₁, a signal generator 14 having function generators 14₋₁, 14₀, 14₁ for generating functions φ₀ (t+T), φ₀ (t), φ₀ (t-T), respectively, a multiplier 15 having three multiplying-type DA converters 15₋₁ ˜15₁ connected to the latch section 13 and signal generator 14, and a mixer 16 for combining a plurality of signals M₋₁, M₀, M₁, which are outputted by the multiplier 15, to produce an analog signal output S_(A).

The digital data generator 10 generates a bit clock BCLK, data latching pulses P_(3N+1) ˜P_(3N+3) and a ROM data latching pulse LCK. The generator 10 also generates, and stores successively in the register 11, the digital data V_(K) (see FIG. 3) of, e.g., 16 bits, at the predetermined time (sampling time) interval T. The frequency of the bit clock BCLK is a·f_(s) (a=64, by way of example) where the sampling frequency is f_(s) (=1/T). The period of the data latching pulses P_(3N+1) ˜P_(3N+3) is 3T, with these latching pulses being successively displaced in phase by T.

The digital signal processor 12 computes the total C of the coefficients indicated in Eq. (8) using the latest nine items of digital data and successively stores the results cyclically in the latch circuits 13₋₁ ˜13₁. More specifically, at the time of time slot T₋₁, a total C₋₁ of the coefficients indicated in Eq. (9) is computed and stored in the latch circuit 13₋₁ ; at the time of time slot T₀, a total C₀ of the coefficients indicated in Eq. (8) is computed and stored in the latch circuit 13₀ ; and at the time of time slot T₁, a total C₁ of the coefficients indicated in Eq. (10) is computed and stored in the latch circuit 13₁. Thereafter, the total value C of the coefficients computed by the digital signal processor 12 is successively stored in the latch circuits 13₋₁ →13₀ →13₁ → . . . as C₋₁, C₀, C₁ whenever new digital data is generated at the sampling period.

FIG. 10 is a block diagram for describing the processing performed by the digital signal processor 12. TD denotes delay circuits for storing digital data during one sampling period T and shifting the data to the next stage. Multipliers are shown at A₋₄ -A₄, and adders are indicated at ADD.

The signal generator 14 includes the aforementioned function generators 14₋₁, 14₀, 14₁ for repeatedly generating signals having the respective functions φ₀ (t+T), φ₀ (t), φ₀ (t-T) of period 3T shown in FIG. 7(a).

FIG. 11 is a block diagram of the function generator 14₋₁. The function generator 14₋₁ includes: a counter 21, which has its count cleared by a reset pulse R_(3N+1) (the same as the data latching pulse P_(3N+1)), and which counts the bit clock signal BCLK of frequency a·f_(s) (where f_(s) is the sampling frequency) and generates an address signal A_(S) of a ROM 22, which is the next stage; the ROM 22, which sequentially stores, in the order of its addresses, the digital values of function φ₀ (t) digitized at the interval 1/(a·f_(s)), and from which the digital data are successively read from storage areas designated by the address signals A_(S) outputted by the counter 21, thereby generating the discrete function φ₀ (t); a latch circuit 23 for latching the digital data outputted by the ROM; a DA converter 24 for converting the output of the latch circuit 23 into a current I₀ having a magnitude proportional to the digital value inputted thereto; a current-voltage converter (IV converter) 25 for converting the current value I₀ from the DA converter 24 into a voltage signal proportional to the current value I₀ ; a low-pass filter 26 for forming the output of the IV converter into a smooth, continuous analog signal; and an amplifier 27. The function generators 14₀, 14₁ have almost the same arrangement as the function generator shown in FIG. 11. The only difference is that the count in counter 21 is reset by the reset pulse R_(3N+2) or R_(3N+3) (the same as data latching pulse P_(3N+2) or P_(3N+3)) instead of the reset pulse R_(3N+1). It should be noted that the function generator 14₋₁ outputs the repeating function φ₀ (t+T) of period 3T from time -T, the function generator 14₀ outputs the repeating function φ₀ (t) of period 3T from time 0, and the function generator 14₁ outputs the repeating function φ₀ (t-T) of period 3T from time T.

The multiplier 15 has the three multiplying-type DA converters 15₋₁ -15₁. The multiplying-type DA converter 15₋₁ multiplies the total value C₋₁ of the coefficients of Eq. (9) stored in the latch circuit 13₋₁ by the function signal φ₀ (t+T) and outputs the product as analog signal M₋₁, the multiplying-type DA converter 15₀ multiplies the total value C₀ of the coefficients of Eq. (8) stored in the latch circuit 13₀ by the function signal φ₀ (t) and outputs the product as analog signal M₀, and the multiplying-type DA converter 15₁ multiplies the total value C₁ of the coefficients of Eq. (10) stored in the latch circuit 13₁ by the function signal φ₀ (t-T) and outputs the product as analog signal M₁.

The mixer 16 has the construction of a well-known analog adder for combining the analog signals M₋₁ ˜M₁ outputted by the multiplying-type DA converters 15₋₁ ˜15₁, thereby producing the output analog signal S_(A).

In accordance with the present invention as described hereinabove, the unit pulse response signal ψ(t) is expressed using simple, short-term functions φ_(k) (t) and coefficients A_(K) in the manner

    ψ(t)=ΣA.sub.K ·φ.sub.K (t) (K=-∞˜+∞)

processing for calculation of A_(K) is performed in advance by a digital signal processor, the function signal φ_(K) (t) is generated as is without being partitioned, the function is multiplied by the coefficients and the results are combined. This makes it possible to generate a continuous analog signal that is free of phase distortion, to reduce the number of circuit units such as the multiplying-type DA converters to three, and to obtain an analog output that is free of noise, has an excellent S/N ratio and exhibits no fluctuation in level.

As many apparently widely different embodiments of the present invention can be made without departing from the spirit and scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims. 

What we claim is:
 1. A digital-analog converting method for converting digital data successively generated every predetermined sampling period T into a continuous analog signal, comprising the steps of:successively generating digital data V_(K) (K=. . . , -4, -3, -2, -1, 0, 1, 2, 3, . . . ) every predetermined sampling period T; repeatedly generating, successively at a period 3T, signals φ(t+T), φ(t), φ(t-T), where a unit pulse response signal ψ(t) is expressed by

    ψ(t)=ΣA.sub.K ·φ(t-K·T) (K=-∞˜+∞)

using a signal φ(t) (0≦t≦3T) expressed by three piecewise polynomials; computing C in accordance with the equation

    C=ΣA.sub.-K ·V.sub.K

(K=-M˜M, where M is an integer)every sampling period T, where V₀ represents digital data prevailing at the present time, and cyclically storing the results of computation as C₋₁, C₀, C₁ in successive fashion; and generating a continuous analog signal by converting the digital data into an analog quantity in accordance with the equation

    C.sub.-1 ·φ(t+T)+C.sub.0 ·φ(t)+C.sub.1 ·φ(t-T)


2. The method according to claim 1, wherein the three piecewise polynomials expressing said signal φ(t) are

    φ(t)=(9/2)·(t/3T).sup.2 (0≦t<T)

    φ(t)=-9·(t/3T-1/2).sup.2 +3/4 (T≦t<2T)

    φ(t)=(9/2)·(t/3T-1).sup.2 (2T≦t<3T)

and A_(K) is expressed by the equation

    A.sub.K =√2(-3+2√2)|K|


3. The method according to claim 2, wherein a value of the signal φ(t) is discretely stored in a ROM beforehand at a time interval of 1/a_(s) of the sampling period T, a bit clock generated at a period 1/a_(s) is counted, numerical values are successively read out of the ROM from addresses indicated by the counted value and the numerical values are converted into voltages to generate the analog signal φ(t), and signals φ(t+T), φ(t-T) are generated in a manner similar to the signal φ(T).
 4. A digital-analog converting apparatus for converting digital data successively generated every predetermined sampling period T into a continuous analog signal, comprising:digital data generating means for successively generating digital data V_(K) (K= . . . , -4, -3, -2, -1, 0, 1, 2, 3, . . . ) every predetermined sampling period T; signal generating means for repeatedly generating, successively at a period 3T, signals φ(t+T), φ(t), φ(t-T), where a unit pulse response signal ψ(t) is expressed by

    ψ(t)=ΣA.sub.K ·φ(t-K·T) (K=-∞˜+∞)

using a signal φ(t) (0≦t≦3·T) expressed by three piecewise polynomials; arithmetic means for computing C in accordance with the equation

    C=ΣA.sub.-K ·V.sub.K

(K=-M˜M, where M is an integer) every sampling period T, where V₀ represents digital data prevailing at the present time; memory means for cyclically storing C, which is computed by said arithmetic means every period T, as C₋₁, C₀, C₁ in successive fashion; three sets of multplying means for respectively computing

    C.sub.-1 ·φ(t+T), C.sub.0 ·φ(t), C.sub.1 ·φ(t-T)

and mixing means for combining outputs from said three sets of multplying means to generate a continuous analog signal.
 5. The apparatus according to claim 4, wherein the three piecewise polynomials expressing said signal φ(t) are

    φ(t)=(9/2)·(t/3T).sup.2 (0≦t<T)

    φ(t)=-9·(t/3T-1/2).sup.2 +3/4 (T≦t<2T)

    φ(t)=(9/2)·(t/3T-1).sup.2 (2T≦t<3T)

and A_(K) is expressed by the equation

    A.sub.K =√2(-3+2√2)|K|


6. The apparatus according to claim 4, wherein a value of the signal φ(t) is discretely stored in a ROM beforehand at a time interval of 1/a_(s) of the sampling period T, a bit clock generated at a period 1/a_(s) is counted, numerical values are successively read out of the ROM from addresses indicated by the counted value and the numerical values are converted into voltages to generate the analog signal φ(t), and signals φ(t+T), φ(t-T) are generated in a manner similar to the signal φ(T).
 7. The apparatus according to claim 6, wherein each of said multiplying means comprises a multiplying-type DA converter. 